ING-INF/05 - 6 CFU - 2° Semester

Teaching Staff


Learning Objectives

The Course objectives are the understanding by students of the major concepts of advanced architectures of microprocessors, the knowledge of the problems and solutions related to the execution of applications., the  knowledge of hardware and software optimization methodologies, the understanding  of the areas of application of different forms of parallelism (instruction-level, data-level, thread-level).

The knowledge gained by the student are used for evaluating the performance of modern microprocessor systems, to exploit the various forms of application parallelism in relation to the characteristics of the different architectures and to propose possible optimizations.

Detailed Course Content

1) Basic Computer Architecture: Pipelined processors (problems and solutions, implementation, Exceptions with pipelined execution), the memory hierarchy and its implementation.

2) Performance Evaluation metrics and optimization techniques: processor and memory.

3) Instruction level parallelism: static and dynamic scheduling, Branch prediction, Hardware-based Speculation, Multi-issue execution. Superscalar architectures: principles and problems; VLIW (Very Long Instruction Word) architectures,  examples of architectures families.

4) Data-level parallelism: vector processors, SIMD extensions; graphics processors, GPGPU

5) Multiprocessors and thread level parallelism: Taxonomy, topologies, communication management, memory management, cache coherence protocols, examples of architectures

Textbook Information

[T1]   Hennessy & Patterson: Computer architecture, a quantitative approach (Morgan Kaufmann eds.) 5 ed.

[T2]  Patterson & Hennessy:  “Struttura e progetto dei calcolatori”. Zanichelli 4. Ed

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