COMPUTER ARCHITECTURE

The course objectives are twofold: Primarily it aims to introduce students to digital systems' technologies. The second objective is the knowledge of computer's organization, Instruction Set Architecture, and common techniques for efficient implementation. At the end of the course, students will be able to design finite state machines and to develop simple programs in the assembly language for MIPS64-based architectures.

Knowledge and understanding

The student will know:

• Basic design techniques for combinatory and sequential digital circuits
• Digital design flow at different abstraction levels
• Digital System main building blocks
• Basics of RISC based processor
• Educational RISC processor assembly Language

Applying knowledge and understanding

The student will be able to:

• Design simple combinational and synchronous sequential circuits
• Apply simple optimization techniques aim to reduce silicon area cost for digital combinational circuits
• Develop models of simple digital systems using the VHDL description language
• Evaluate the performance of a computer and the impact of architectural choices on performances
• Write programs in the assembly language of an educational processor

Making judgements

The student will be able to assess the impact of architectural choices on the performance of a computer.

Learning skills

The student will be able to be autonomous for understanding:

• Further hardware description languages
• Assembly language for different RISC processors

The main teaching methods are lectures, aimed at providing the basic theoretical knowledge, and exercises, proposed and solved by the teacher, aimed at improving student’s “problem solving” skills.

If the teaching is given in a mixed or remote mode, the necessary changes with respect to what was previously stated may be introduced, to respect the program planned and reported in the syllabus.

Part I – Digital Design

1.1 Design of Combinational Logic Networks:
Switching algebra. Minimum Boolean expressions. Minimisation with Karnaugh maps.

1.2 Design of synchronous circuits:
Introduction to sequential machines. Memory elements: flip-flops. Synthesis of synchronous circuits. Minimisation of Finite State Machines.

1.3 Digital systems design:
Design flow of a digital system. Datapath and Control Unit. Hardware description languages: VHDL.

1.4 Digital Integrated Circuits design flow briefly

Logic Synthesis, Place and Route and FPGA.

Part II – Computers

2.1. Computer organization:
Computer organization. Computer Performance Evaluation Techniques. Instruction Set Architecture. Sequential processors. Datapath of a sequential processor. Control Unit of a sequential processor: hard-wired and microprogrammed logic.

2.2. Process Control Unit:
Instruction execution and straight-line sequencing. Single-cycle CPU. Multi-cycle CPU. Development of control logic. Considerations on multi-cycle implementation.

2.3. Pipeline
Pipeline properties. Pipeline execution. Execution phases. Hazards: data hazards, control hazards, and structural hazards.

2.4. The memory subsystem:
Static and dynamic RAM memories. Asynchronous and synchronous memories. Memory organisation. Cache memories. Evaluation of memory performance.

2.5. The Input/output subsystem:
Polling. Interrupts. Vectored Interrupts. Priority management. Direct Memory Access.

2.6. Assembly language:
Assembler, linker, and loader. MIPS64 Instruction Set Architecture. Instruction Set Simulator for the EduMIPS64 processor. Assembly of the EduMIPS64 processor. Array management. Procedures.

[T1] Fummi, Sami, Silvano, "Progettazione digitale", 2a edizione, McGraw-Hill;

[T2] Patterson, Hennessey, “Computer Organization and Design RISC-V Edition: The Hardware Software Interface”, Morgan Kaufmann.

[T3] Support material provided during the course.