COMPUTER ARCHITECTURE M - Z

The course has two goals.

It introduces the knowledge of the technologies and methodologies for the design of digital systems at different levels of abstraction. The student learns to design digital systems.

The second objective is the knowledge of the organization of a computing system, the architecture of the instruction set, and the techniques for an efficient implementation. In this context the student learns to evaluate the performance of a computer and the impact of architectural choices on performance. Moreover, the student lerns to program in the Assembly language of an educational processor.

The course will be organized in lectures, exercises, practical experiences and presentation of use cases.

Part I Digital Design

1.1 Combinational circuits design

Switching Algebra. Minimum Boolean expressions. Minimization using Karnaugh maps and Quine-McCluckey method.

1.2 Synchronous sequential circuits Design

Introduction to sequential machines. The memory elements. Synthesis of synchronous sequential circuits. Minimization of finite state machines.

1.3 Design of a digital system

Design flow of a digital system. Datapath and control unit. Hardware description Languages. VHDL. Entity and architecture. Concurrent and sequential models. Process. Data types. Procedure and funtions. Simulations and synthesis.

Part II Computer architecture

2.1 Computer abstractions and technology

The types of computers and their characteristics. The components of a computer. Computer Organization. Computer performance evaluation. Amdhal’s law.

2.2 The computer language: the Assembly

Instruction Set Architecture. Translation and starting a program: assembler, linker, and loader. MIPS64 Instruction Set Architecture. An educational Instruction Set Simulator for MIPS 64 processor: EDUMIPS. Assembly of EduMIPS64 processor. Arithmetic/logical instructions. Memory access. System calls. Array. String. Procedure calls

2.3 Computer Organization

Sequential organization of a processor. Datapath of a sequential processor. Control unit of a sequential processor.

Organization of pipelined processor. Pipeline Hazard. Performance evaluation of a pipelined processor. Techniques for detecting and resolving pipeline hazards. Code scheduling for hazard minimization.

2.4 The Memory subsystem.

Static and dynamic RAM memories. Asynchronous and synchronous memories. Memory organization.

Cache memories. Block placement policies, block identification, block replacement and write policy. Memory Performance. Techniques for improving cache performance.

[T1] Fummi, Sami, Silvano, “Progettazione digitale”, 2/ed McGraw-Hill

[T2] Patterson, Hennessy, “Struttura e progetto dei calcolatori”, Zanichelli

[T3] Bucci, “Architettura e organizzazione dei calcolatori elettronici: fondamenti”, McGraw-Hill

[T4] On line Course material