The Course objectives are the understanding by students of the major concepts of advanced architectures of microprocessors, the knowledge of the problems and solutions related to the execution of applications., the knowledge of hardware and software optimization methodologies, the understanding of the areas of application of different forms of parallelism (instruction-level, data-level, thread-level).
The knowledge gained by the student are used for evaluating the performance of modern microprocessor systems, to exploit the various forms of application parallelism in relation to the characteristics of the different architectures and to propose possible optimizations.
The course will be organized in lectures and exercises.
1) Basic Computer Architecture:
Pipelined processors (problems and solutions, implementation)
Branch prediction
Exceptions with pipelined execution)
The memory hierarchy and its implementation.
2) Instruction level parallelism
Static and dynamic scheduling.
Hardware-based Speculation, Multi-issue execution. Superscalar architectures: principles and problems.
VLIW (Very Long Instruction Word) architectures, examples of architectures families.
3) Data-level parallelism
Vector processors.
SIMD extensions.
Graphics processors, GPGPU
4) Multiprocessors and thread level parallelism
Taxonomy, topologies, communication management, memory management.
Cache coherence protocols, examples of architectures
[T1] Hennessy & Patterson: Computer architecture, a quantitative approach (Morgan Kaufmann eds.) 5 ed.
[T2] Patterson & Hennessy: “Struttura e progetto dei calcolatori”. Zanichelli 4. Ed